Use the electromotive force splitter biasing method to put the DC operating point ( VGSq, IDSq ) . Verify the estimated DC runing point with the measured informations.
Investigate the consequence of frequence alterations on the electromotive force addition of the amplifier, step its frequence response and obtain its operating bandwidth.
Investigate the electrical capacity consequence on the frequence response of the common beginning JFET amplifier
All related computation inquiries that does non necessitate experimental informations must be answered before coming to the lab. You are required to demo all the computation stairss when requested by the lab teacher. During the rating session, your lab teacher may bespeak you to show how the measuring informations is obtained and explicate your experimental consequences.
You are advised to try the theoretical inquiries asked in the lab sheet before coming to the lab. The lab session is merely 3 hours and will be largely spend on roll uping experiment informations, analysing consequence and comparing the information with the deliberate value. Before coming to the lab, you will besides necessitate to analyze the related theory from lecture stuff of chapter 1 and subjects affecting JFET device feature, JFET biasing and JFET amplifier from the text edition. This is of import so that you know what consequence will be expected from the experiment. In order to reply the inquiries in the labsheet, you besides need to do reading readying.
An amplifier is a circuit that increases/decrease the input signal value and in this experiment the signal to be amplified is the electromotive force. In this experiment you are traveling to look into frequence response feature of a electromotive force amplifier circuit utilizing the N-channel JFET device
Most amplifiers have comparatively changeless addition over a certain scope of frequences. This scope of frequences is called the bandwidth of the amplifier. The bandwidth for a given amplifier depends on the circuit constituent values, the type of active constituents and the District of Columbia runing point of the active constituent. When an amplifier is operated within its bandwidth, the current addition, electromotive force addition, and power addition values are referred to as midband addition values. A simplified frequency-response curve that represents the relationship between amplifier addition and operating frequence is shown in Figure 1.
Ap beads at lower frequences
Ap beads at higher frequences
0.5Ap ( mid )
Ap ( mid )
Figure 1: A simplified frequence response curve
As the frequency-response curve shows, the power addition of an amplifier remains comparatively changeless across a set of frequences. When the operating frequence starts to travel outside this frequence scope, the addition begins to drop. Two frequences of involvement, and, are the frequences at which power addition lessenings to about 50 % of. The frequences labeled and are called the lower and upper cutoff frequences of an amplifier, severally. These frequences are considered to be the bandwidth bounds for the amplifier and therefore bandwidth BW is given by
The geometric norm of and is called the geometric centre frequence field-grade officer of an amplifier, given by
When the operating frequence is equal to, the power addition of the amplifier is at its maximal value.
Frequency response curves and specification sheets frequently list addition values that are measured in dBs ( dubnium ) . The dB power addition of an amplifier is given by
Positive and negative dBs of equal magnitude represent mutual additions and losingss. A +3dB addition caused power to duplicate while a -3dB addition caused power to be cut in half.
Using the basic power relationships, and, the power addition may be rewritten as
The electromotive force constituent of the equation is referred to as dB electromotive force addition. When the amplifier input and out oppositions are equal
. ( )
Therefore, when the electromotive force addition of an amplifier alterations by -3dB, the power addition of the amplifier besides alterations by -3dB.
Low Frequency Response of FET Amplifier
In the low frequence part of a individual phase FET amplifier as shown in Figure 2 ( a ) , it is the RC combinations formed by the web capacitances and the web resistive parametric quantities that determine the cutoff frequence. There are three capacitances – two matching capacitance and, and one beltway capacitance, . Let us presume that, and are randomly big and can be represented by short-circuit. The entire opposition in series with is given by
where is the input electric resistance of the amplifier circuit. The power supplied by the signal generator is. However, the reactance XCG of electrical capacity is non negligible at really low frequences. The frequence at which Pin is cut in half is when. Thus the lower half-power point for gate circuit occurs at frequence
Figure 2 ( a ) : Conventional diagram of a JFET amplifier.
Figure 2 ( B ) : JFET amplifier low-frequency ac equivalent circuit
Figure 2 ( degree Celsius ) : Approximate drain circuit of JFET amplifier ( presuming the opposition of the JFET drain terminus, rd, is much larger than RD ) .
When and are randomly big and can be represented by short-circuit, the drain circuit of the JFET amplifier is as shown in Figure 2 ( degree Celsius ) . At high frequence where Cadmium can besides be represented by a short-circuit, the end product power to lade resistance RL is. At low frequences where the reactance XCD of electrical capacity is non negligible, Pout is cut in half when. Thus the lower half-power point for drain circuit occurs at frequence
At the half-power point, the end product electromotive force reduces to 0.707 times its midband value. The existent lower cutoff frequence is the higher value between fLG ( determined by CG ) and fLD ( determined by Cadmium ) .
High Frequency Response of FET Amplifier
The high frequence response of the FET is limited by values of internal electrical capacity, as shown in Figure 3 ( a ) . There is a mensurable sum of electrical capacity between each terminal brace of the FET. These electrical capacities each have a reactance that decreases as frequence additions. As the reactance of a given terminal electrical capacity lessenings, more and more of the signal at the terminus is bypassed through the electrical capacity.
Figure 3 ( a ) : JFET amplifier with internal capacitances that affect the high frequence response.
Cout ( M )
Cin ( M )
Figure 3 ( B ) : FET amplifier high frequence ac tantamount circuit.
The high frequence tantamount circuit for the FET amplifier in Figure 3 ( a ) is shown in Figure 3 ( B ) , including all the terminal electrical capacity values. is replaced with the Miller equivalent input and end product electrical capacity values given as
Cin ( M )
Cout ( M )
Figure 4: Miller equivalent circuit for a feedback capacitance
Note the absence of capacitances, , and in Figure 3 ( B ) , which are all assumed to be short circuit at high frequences. From this figure, the gate and drain circuit electrical capacity are given by
where is the input electrical capacity of the undermentioned phase. In general the electrical capacity is the largest of the parasitic electrical capacities, with the smallest. The high cutoff frequences for the gate and drain circuits are so given by
where and. At really high frequences, the consequence of is to cut down the entire electric resistance of the parallel combination of, , and in Figure 3 ( B ) . The consequence is a decreased degree of electromotive force across the gate-source terminuss. Similarly, for the drain circuit, the capacitive reactance of will diminish with frequence and accordingly reduces the entire electric resistance of the end product parallel subdivisions of Figure 3 ( B ) . It causes the end product electromotive force to diminish as the reactance becomes smaller.
Before linking the circuit of Figure 5, step the existent opposition of R1, R2, RD, RS and RL every bit accurate as possible with a digital multimeter ( put it to the best opposition scope ) and enter the mensural values.
Connect the common beginning JFET amplifier circuit as shown in Figure 5 utilizing a bread board ( mention to Appendix C ) . Do non link the power supply and the map generator to the circuit yet. Keep the connecting wires on the bread board every bit short as possible ( & lt ; 3 centimeter ) to cut down unwanted induction and electrical capacity in your circuit.
Put the power supply end product to +12V. Connect its end product to the circuit and step its electromotive force VDD ( meas ) every bit accurate as possible with the multimeter. Calculate the gate DC electromotive force VG ( cal ) utilizing the voltage-divider regulation.
Measure the DC electromotive forces VG, VD and VS at G, D, and S pins of the transistor every bit accurate as possible. Note that the mensural VG should be closed to the deliberate VG ( cal ) , and VS should be & gt ; VG since VGS must be & lt ; 0 V for N-channel JFET.
Before linking the map generator to the circuit, use an CRO to mensurate the end product electromotive force of the generator and put it to 200 kilohertzs sine-wave with a peak-to-peak electromotive force of 0.1V. Press the fading button ( ATT ) of the generator for easy accommodation of its end product electromotive force.
Connect the generator end product to the circuit. Using Channel 1 ( CH1 ) of the CRO ( set at AC input matching ) , probe the input electromotive force vin. Using Channel 2 ( CH2 ) of the CRO, probe the burden resistance RL, as shown in Figure 5. Put the trigger beginning of the CRO to CH2. Adjust the trigger degree on the CRO to obtain stable wave forms. Make certain the variable ( VAR ) boss of the CRO are set at the calibrated ( CAL ‘D ) places.
( vL )
( vin )
Figure 5: A common beginning JFET amplifier
Adjust the Volts/div and Time/div to expose the wave forms on the CRO screen every bit large as possible with one to two rhythms. Sketch the input AC electromotive force ( vin ) and the burden electromotive force ( vL ) waveforms on the graph. Record the Time/div and Volts/div used. Note that the input and end product wave forms should be about 180o out of stage.
From your graph, find VL ( pp ) and Vin ( pp ) which are the peak-to-peak electromotive forces of vL and vin, severally. Calculate the electromotive force addition ( Av ) of the JFET amplifier circuit at 200 kilohertz. Ask the teacher to look into all of your consequences. You must demo the CRO waveforms to the teacher.
Brush the frequence of the map generator from 1 kilohertzs to 550 kilohertzs ( utilize smaller frequence stairss near the half-power point while larger stairss can be used at mid-band frequences ) . Record the peak-to-peak electromotive forces of vin ( CH1 ) and vL ( CH2 ) and cipher the dB magnitude of the electromotive force addition Av. Use both coarse and all right accommodation boss of the map generator for frequence accommodation.
Plot a curve of Av versus frequence.
Calculate the lower cutoff frequence fLD ( cal ) ( use the measured RD and RL values ) . Put the frequence to 20 kilohertzs. To mensurate the lower cutoff frequence ( fLD ) , decrease the generator frequence until VL ( pp ) decreases to 0.707VL, mid-band ( pp ) , where VL, mid-band ( pp ) is the VL ( pp ) value in the mid-band.
Set the frequence to 300 kilohertzs. To mensurate the upper cutoff frequence ( fHD ) , increase the generator frequence until VL ( pp ) decreases to 0.707VL, mid-band ( pp ) .
Determine the bandwidth ( BW ) and the geometric centre frequence ( fo ) of the amplifier from the above measurings. Ask the teacher to look into all of your consequences. You must demo the CRO waveforms at 550 kilohertz to the teacher.
Design or modify the circuit in Figure 5 in order to mensurate the parametric quantity of the device, viz. Gate-Source Cutoff Voltage ( VGS ( off ) or Vp ) and Zero-Gate Voltage Current ( IDSS ) . These two values can be used in the Shockley equation ID = IDSS ( 1 – VGS/Vp ) 2. Hint: You can utilize a potentiometer and/or negative power beginning in the circuit. By work outing the coincident equation of the Shockley equation and the burden line equation, you can obtain the deliberate value for the Q point VGSQ, VDSQ, IDQ. . Compare this with the measured value.
Submit your study on the same twenty-four hours instantly after the experiment.
Appendix A – Planing Voltage-Divider Bias for JFET
Similar to planing a bipolar transistor circuit, a JFET needs to be biased at the right District of Columbia runing point before it can work decently as an amplifier. There are a figure of biasing constellations available, such as gate prejudice, self-bias, and voltage-divider prejudice. The self-bias and the voltage-divider prejudice usage negative District of Columbia feedback to stabilise the operating point of the JFET against parameter fluctuation of the JFET. DC runing point in this context refers to the drain-to-source electromotive force VDS and the drain current ID of the JFET. A stable operating point means VDS and ID do non alter much with temperature and when we change one JFET with another JFET of similar portion figure. A voltage-divider prejudice using the general purpose N-channel JFET 2N5457 is shown in Figure A1.
Figure A1 – Schematic of the District of Columbia prejudice utilizing voltage-divider prejudice strategy
A.1 JFET Large Signal Parameters
From the datasheet of 2N5457, the undermentioned parametric quantities are given at temperature of 25oC.
Table A1 – Minimum and maximal big signal parametric quantity for 2N5457
Gate Source Cutoff Voltage ( VT )
-0.5V ( VTmin )
-6.0V ( VTmax )
Zero-Gate Voltage Drain Current ( IDSS )
1.0mA ( IDSSmin )
5.0mA ( IDSSmax )
A.2 Transconductance Curve
When the JFET is biased in its active part, the channel between drain and beginning terminuss is in “ pinched-off ” province. The drain current will be mostly independent of the drain-source electromotive force VDS and will merely depend on the gate-source electromotive force VGS. Therefore unlike the bipolar transistor which is a current controlled device ( the aggregator current IC is a map of base current IB in active part ) , the JFET or FET in general is a electromotive force controlled device. The relationship between VGS and ID in the active part is given by:
( 1 )
Ploting ( 1 ) for the two sets of big signal parametric quantity ( VTmin, IDSSmin ) and ( VTmax, IDSSmax ) consequences in the curves of Figure A2. These curves are known as transconductance curves because they relate current to electromotive force.
IDmax refers to the curve when parametric quantities is given by ( VTmax, IDSSmax ) while IDmin for parametric quantity ( VTmin, IDSSmin ) .
Figure A2 – The transconductance curve for the JFET 2N5457
A.3 Determining the Load Line
From Figure A1, ( 2 )
and ( 3 )
Since ( 4 )
Substituting ( 3 ) into ( 4 ) , we obtain the burden line relationship:
( 5 )
Equation ( 5 ) is in the signifier
So it is a consecutive line where m is the gradient of incline of the line and degree Celsius is the intercept point of the line with the ID axis.
Let us choose ( ID_max, VGS_max ) and ( ID_min, VGS_min ) to be the two desired operating points on the upper limit and minimal transconductance curves. This is shown in Figure A3. A consecutive line can be drawn fall ining these two points ; this line will be our dc burden line. The incline and intercept point of the line will find the value of biasing resistances R1, R2 and RS. The value of ID_max and ID_min are selected based on the allowable alteration in drain current due to parameter fluctuation in the JFET.
( VGS_max, ID_max )
( VGS_min, ID_min )
Required dc burden line
Allowable alteration in drain current ID due to parameter fluctuation.
Figure A3 – Required upper limit and lower limit operating points and the District of Columbia burden line
The lone demand for the two operating points would be:
|ID_max| & gt ; |ID_min| ( 6 )
A.4 Finding the Values of Bias Resistors
The process of planing the voltage-divider prejudice for JFET is now summarized as follows:
Fix ID_max and ID_min, the drain current at the upper limit and minimal transconductance curves. This will find the allowable alteration in drain current.
Find VGS_max and VGS_min.
( 7a )
( 7b )
Determine the incline and intercept point for dc burden line, from ( 5 ) .
( 8a )
( 8b )
( 9 )
( 10 )
Arbitrary taking a suited R2. Then R1 is given by, from ( 2 ) :
( 11 )
Choose a suited value for RD. Find the corresponding drain electromotive force.
( 12a )
( 12b )
Example – For this Lab Experiment
From Figure A3, we would wish the District of Columbia burden line to stop the upper limit and minimal transconductance curves when VGS is negative. From Equation ( 6 ) , allow us take:
ID_max = 1.50mA
ID_min = 0.85mA
From ( 7a ) and ( 7b ) :
VGS_max = -2.714V
VGS_min = -0.039V
From ( 8a ) and ( 8b ) :
m = -2.430i‚?10-4
hundred = 8.405i‚?10-4
Hence from ( 9 ) :
RS = 4.12ki?- .
And from ( 10 ) :
VG = 3.46V
Finally from taking R2 = 10.0ki?- :
from ( 11 ) , R1 = 24.7ki?-
If we choose a drain opposition of RD = 3.3ki?- , from ( 12a ) and ( 12b )
VD_max = 9.20V
VD_min = 7.05V
Percentage mistake in drain electromotive force ;
Mistake = ( 9.20 – 7.05 ) / 7.05 = 22.33 %
A secret plan of the burden line is shown in Figure A4.
Dc burden line
Figure A4 – Dc load line with transconductance curves for illustration